1. Field of the Invention
The present invention relates to a parallel signal processing circuit capable of parallel processing a plurality of signals input from a plurality of input terminals, a semiconductor device having the circuit, and a signal processing system having the circuit.
2. Related Background Art
In a conventional semiconductor device that performs parallel arithmetic operation processing, as the number of signals to be subjected to parallel arithmetic operations increases, the circuit scale increases in progression, resulting in an increase in manufacturing cost and a decrease in yield. As the circuit scale increases, the arithmetic operation speed lowers owing to an increase in delay time caused by wiring lines, and an increase in the number of arithmetic operations in the circuit. Furthermore, the consumption power increases considerably.
For example, in the case of a solid-state imaging device shown in FIG. 1, image signals are read out by a scanning circuit from a sensing unit 60 serving as an area sensor constituted by a two-dimensional array of imaging elements 41, and these time-series analog signals are converted into digital signals by an A/D converter 40. The digital signals are temporarily stored in a frame memory 39. The multi-input terminal signals read out from the frame memory 39 are subjected to arithmetic operation processing by an arithmetic operation circuit 38, and the arithmetic operation result is output from an arithmetic operation output circuit 50. More specifically, the moving amount (.DELTA.X, .DELTA.Y) of an object can be output by correlation arithmetic operations of data at different times.
However, in order to perform real-time processing of a moving image, the number of processing steps of the arithmetic operation processing is very large, and the circuit scale increases in progression to obtain a real image, resulting in low processing speed. For example, an apparatus that can actually process the MPEG2 method proposed as a moving image compression/expansion method has been under development. Therefore, as the problems of the above-mentioned parallel arithmetic operation processing, the problems of a decrease in arithmetic operation speed, and an increase in consumption power are posed. These problems also cause an increase in manufacturing cost and a decrease in manufacturing yield.
On the other hand, a majority arithmetic operation circuit suitable for a parallel arithmetic operation processing circuit is described in "Economic Majority Logic IC Realized by CMOS", Nikkei Electronics, Nov. 5, 1973, pp. 132-144. However, a majority logic circuit is disclosed as one of digital signal processing operations, and is formed by a CMOS circuit. In this case as well, since the number of elements of the CMOS circuit increases, and the number of arithmetic operation processing steps increases, the problem of a decrease in arithmetic operation speed is posed in addition to increases in circuit scale and consumption power.